A digital signal processor (DSP) instruction set typically include multiply-accumulate instructions which execute in dedicated hardware. This multiply-accumulate hardware implements the function:Acc<=Acc+(X*Y).
As defined above the multiply-accumulate instruction forms the product of two operands X and Y and adds their product to the value stored in an accumulator. The sum is stored in the accumulator overwriting the previous value.
It is desirable to have load or move instructions having this accumulation register (Acc) as a destination. Implementing this function typically employs a multiplexer between data from the multiply-accumulate result and the load/move data. The prior art places this multiplexer just before the Acc register. This places the multiplexer on the most critical path. This critical path is the data flow from the X/Y source registers, through the multiply and add operations to the Acc register.
The multiplexer placement creates a problem. By being in the critical path, the multiplexer slows operation of the multiply-accumulate function. The prior art placement of the multiplexer causes all operations to slow, even ordinary multiply-accumulation. This limits the clock rate that can be employed potentially slowing all data processor operation.